The present invention relates to physical design technology for an integrated circuit like CMOS or LSI.
In a known design process, a library of cells, causing delays of various lengths or having mutually different areas, is prepared for a circuit being designed to optimize the performance setting parameters of the circuit such as area, power dissipation and operating clock frequency. According to a method of this type, trial-and-error is inevitable before desired circuit performance is realized. That is to say, a combination of cells should be changed many times for that purpose. Also, to accurately estimate a characteristic value (e.g., wire capacitance) that is changeable depending on the layout adopted and will have a considerable effect on the resultant performance of an integrated circuit, the cell layout and replacement process is sometimes carried out repeatedly.
In any cell included in an integrated circuit being designed, the best specifications for realizing the desired performance are subject to change with various external conditions (e.g., load capacitance and drive) imposed on the cell. According to the known design process, however, an integrated circuit is designed using an existent cell library. Thus, not every cell in such a library is best suited for a given integrated circuit considering the external conditions thereof. In other words, it is not always possible to realize the best performance for each and every integrated circuit with a common library like this. Nevertheless, a design process should include a huge number of process steps if a broad variety of cells were prepared for a library while taking actual external conditions into account more fully.
It is therefore an object of the present invention to optimize the performance of an integrated circuit being designed much more efficiently.
Specifically, an inventive physical design method is applicable to an integrated circuit made up of multiple cells. The method includes the steps of: a) evaluating the overall performance of the integrated circuit; b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and c) changing the performance of the candidate cell selected in the step b). In the step c), a characteristic representing the performance of the candidate cell is determined in view of an external condition imposed on the candidate cell.
According to the present invention, a performance characteristic is determined for a cell, selected as a candidate cell, in view of an external condition imposed thereon. Thus, the performance characteristic of the cell can be estimated much more accurately. As a result, the overall performance of the integrated circuit being designed can be optimized.
In one embodiment of the present invention, the performance of the cell is preferably changed in the step c) by reference to a library, on which information about the respective cells is stored and on which two or more mutually different performance characteristics, associated with a single external condition, are stored for at least one of the cells. If two or more mutually different performance characteristics, associated with the external condition imposed on the candidate cell, are stored on the library, one of these performance characteristics is preferably selected.
In another embodiment of the present invention, the external condition imposed on the candidate cell preferably includes at least one of output load capacitance, input drive and input waveform. In still another embodiment, parameters representing the performance characteristic of the candidate cell preferably include at least one parameter selected from the group consisting of delay, area, power dissipation, output drive and input load capacitance.
Another inventive physical design method is also applicable to an integrated circuit made up of multiple cells. The method includes the steps of: a) evaluating the overall performance of the integrated circuit; b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and c) changing the performance of the candidate cell selected in the step b). The steps a), b) and c) are performed repeatedly. And in the step a), one of multiple evaluating approaches prepared is selected on a predetermined condition and the performances of the cells, included in the integrated circuit, are evaluated by the approach selected.
According to the present invention, the performances of cells, included in an integrated circuit, are evaluated by an approach selected from multiple approaches on a predetermined condition. Thus, the processing speed can be increased without decreasing the accuracy of cell performance estimation.
In one embodiment of the present invention, according to one of the approaches, the size of transistors, which make up each said cell, is preferably optimized with the area and performance of the cell taken into account. And then the performance of the cell, made up of the transistors of the optimized size, is evaluated.
In an alternative embodiment, according to another one of the approaches, the performance of at least one of the cells is preferably evaluated by reference to a library, on which information about the respective cells is stored and on which two or more mutually different performance characteristics are stored for the cell, and by interpolating and approximating the two or more performance characteristics.
In another embodiment, the predetermined condition may be presented considering at least priority levels of a specified length of a design process and target performance of the integrated circuit.
Alternatively, the predetermined condition may also be presented considering at least the number of times the steps a) through c) should be performed repeatedly.
In still another embodiment, the performance of each said cell may be evaluated in the step a) by reference to a library on which various performance characteristics, associated with respective external conditions, are stored for at least one of the cells. In that case, the predetermined condition is preferably presented considering at least difference between an external condition currently imposed on the cell and the external condition stored on the library for the same cell.
In yet another embodiment, the performance of each said cell may also be evaluated in the step a) by reference to a library on which size information is stored as one of the performance characteristic. In that case, the predetermined condition is preferably presented considering at least difference between information about the current size of the cell and the size information stored on the library for the same cell.
In yet another embodiment, the performance of each said cell may also be evaluated in the step a) by reference to a library on which the performance characteristics of the respective cells are stored. In that case, an alternative performance characteristic, which has been obtained for the cell as a result of the performance evaluation, is preferably newly registered with the library. In this manner, the performance characteristic of each cell can be more accurately estimated by reference to a library without increasing the number of process steps needed for building up a library.
Still another inventive physical design method is also applicable to an integrated circuit made up of multiple cells. The method includes the steps of: a) determining relative positions of the cells and wires interconnecting the cells together in the integrated circuit; b) evaluating a performance of the integrated circuit; c) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step b); and d) changing the performance of the candidate cell selected in the step c). The steps b), c) and d) are performed repeatedly. No matter how many times the steps b) through d) are performed, the same relative positions of the cells and wires, determined in the step a), are maintained.
According to the present invention, the same relative positions are maintained for cells and wires throughout the design process of an integrated circuit. Thus, the performance of an integrated circuit, which usually changes depending on the particular layout, can be estimated accurately, and an optimum solution can be obtained without getting stuck in a local solution or infinite loop.
In one embodiment of the present invention, the relative positions of the cells and wires may be determined in the step a) so that the area of the integrated circuit is minimized.
In another embodiment of the present invention, the relative positions of the cells and wires may be determined in the step a) so that the cells are placed at a uniform density in the integrated circuit.
In still another embodiment, the cells may be arranged in columns and rows in the step a). In the step b), the area of the integrated circuit may be estimated from a product of a maximum cell row length and a maximum cell column length.
In yet another embodiment, it may be estimated in the step b) how the shape of at least one of the wires changes when the area of the cell, having had its characteristic changed in the step d), changes. In that case, the performance of the integrated circuit is preferably evaluated while taking the estimated wire shape change into account.
Yet another inventive physical design method is also applicable to an integrated circuit made up of multiple cells. The method includes the steps of: a) evaluating the overall performance of the integrated circuit; b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and c) changing the performance of the candidate cell selected in the step b). The steps a), b) and c) are performed repeatedly. Each said cell should have a minimum area initially. And in the step c), the performance of the candidate cell is changed by allowing the candidate cell to just increase its area.
According to the present invention, each cell may have its performance changed so that its area just increases. That is to say, the performance of the cell can be estimated with its computational complexity reduced. As a result, the processing speed increases.
Yet another inventive physical design method is also applicable to an integrated circuit made up of multiple cells. The method includes the steps of: a) evaluating the overall performance of the integrated circuit; b) selecting, as a candidate cell that should have its performance changed, at least one of the cells from the integrated circuit based on a result of the step a); and c) changing the performance of the candidate cell selected in the step b). The steps a), b) and c) are performed repeatedly. And in the step a), the size of transistors, which make up each said cell, is optimized with the area and performance of the cell taken into account, and then the performance of the cell, made up of the transistors of the optimized size, is evaluated.